"Joint AGC-Equalization Algorithm and VLSI Architecture for Wirelined ..."

Jyh-Ting Lai, An-Yeu Wu, Chien-Hsiung Lee (2007)

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DOI: 10.1109/TVLSI.2007.893593

access: closed

type: Journal Article

metadata version: 2020-03-11

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Jyh-Ting Lai, An-Yeu Wu, Chien-Hsiung Lee:
Joint AGC-Equalization Algorithm and VLSI Architecture for Wirelined Transceiver Designs. IEEE Trans. Very Large Scale Integr. Syst. 15(2): 236-240 (2007)

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