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Chien-Hsiung Lee

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2000 – 2009

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2007
[j1]
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Jyh-Ting Lai, An-Yeu Wu, Chien-Hsiung Lee:
Joint AGC-Equalization Algorithm and VLSI Architecture for Wirelined Transceiver Designs. IEEE Trans. Very Large Scale Integr. Syst. 15(2): 236-240 (2007)
2001
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Shyh-Jye Jou, Shu-Hua Kuo, Jui-Ta Chiu, Chu King, Chien-Hsiung Lee, Tim Liu:
A serial link transceiver for USB2 high-speed mode. ISCAS (4) 2001: 72-75

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