![](https://dblp.uni-trier.de./img/logo.ua.320x120.png)
![](https://dblp.uni-trier.de./img/dropdown.dark.16x16.png)
![](https://dblp.uni-trier.de./img/peace.dark.16x16.png)
Остановите войну!
for scientists:
![search dblp search dblp](https://dblp.uni-trier.de./img/search.dark.16x16.png)
![search dblp](https://dblp.uni-trier.de./img/search.dark.16x16.png)
default search action
"Special issue on BIT CMOS built-in test architecture for high-speed jitter ..."
Karen Taylor et al. (2005)
- Karen Taylor, Bryan Nelson, Alan Chong, Henry C. Lin, Eddie Chan, Mani Soma, Hosam Haggag, Jeff Huard, Jim Braatz:
Special issue on BIT CMOS built-in test architecture for high-speed jitter measurement. IEEE Trans. Instrum. Meas. 54(3): 975-987 (2005)
![](https://dblp.uni-trier.de./img/cog.dark.24x24.png)
manage site settings
To protect your privacy, all features that rely on external API calls from your browser are turned off by default. You need to opt-in for them to become active. All settings here will be stored as cookies with your web browser. For more information see our F.A.Q.