"Fast HUB Floating-Point Adder for FPGA."

Julio Villalba, Javier Hormigo, Sonia González-Navarro (2019)

> Home

Details and statistics

DOI: 10.1109/TCSII.2018.2873194

access: closed

type: Journal Article

metadata version: 2025-01-19

- view
  - electronic edition via DOI
  - unpaywalled version
  authority control:
- export record
  dblp key:
  - journals/tcas/VillalbaHG19
- ask others
- share record
  persistent URL:
  - https://dblp.org/rec/journals/tcas/VillalbaHG19
Julio Villalba, Javier Hormigo, Sonia González-Navarro:
Fast HUB Floating-Point Adder for FPGA. IEEE Trans. Circuits Syst. II Express Briefs 66-II(6): 1028-1032 (2019)

manage site settings

To protect your privacy, all features that rely on external API calls from your browser are turned off by default. You need to opt-in for them to become active. All settings here will be stored as cookies with your web browser. For more information see our F.A.Q.