"Efficient VLSI Architecture for Decimation-in-Time Fast Fourier Transform ..."

Pramod Kumar Meher et al. (2015)

> Home

Details and statistics

DOI: 10.1109/TCSI.2015.2495724

access: closed

type: Journal Article

metadata version: 2020-05-22

- view
  - electronic edition via DOI
  - unpaywalled version
  authority control:
- export record
  dblp key:
  - journals/tcas/MeherMPGS15
- ask others
- share record
  persistent URL:
  - https://dblp.org/rec/journals/tcas/MeherMPGS15
Pramod Kumar Meher, Basant Kumar Mohanty, Sujit Kumar Patel, Soumya Ganguly, Thambipillai Srikanthan:
Efficient VLSI Architecture for Decimation-in-Time Fast Fourier Transform of Real-Valued Data. IEEE Trans. Circuits Syst. I Regul. Pap. 62-I(12): 2836-2845 (2015)

manage site settings

To protect your privacy, all features that rely on external API calls from your browser are turned off by default. You need to opt-in for them to become active. All settings here will be stored as cookies with your web browser. For more information see our F.A.Q.