"Computing the Soft Error Rate of a Combinational Logic Circuit Using ..."

Rajeev R. Rao et al. (2007)

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DOI: 10.1109/TCAD.2007.891036

access: closed

type: Journal Article

metadata version: 2020-09-24

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Rajeev R. Rao, Kaviraj Chopra, David T. Blaauw, Dennis Sylvester:
Computing the Soft Error Rate of a Combinational Logic Circuit Using Parameterized Descriptors. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 26(3): 468-479 (2007)

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