"Test Schedule Optimization for Multicore SoCs: Handling Dynamic Voltage ..."

Xrysovalantis Kavousianos et al. (2012)

> Home

Details and statistics

DOI: 10.1109/TCAD.2012.2203600

access: closed

type: Journal Article

metadata version: 2022-01-03

- view
  - electronic edition via DOI
  - unpaywalled version
  authority control:
- export record
  dblp key:
  - journals/tcad/KavousianosCJP12
- ask others
- share record
  persistent URL:
  - https://dblp.org/rec/journals/tcad/KavousianosCJP12
Xrysovalantis Kavousianos, Krishnendu Chakrabarty, Arvind Jain, Rubin A. Parekhji:
Test Schedule Optimization for Multicore SoCs: Handling Dynamic Voltage Scaling and Multiple Voltage Islands. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 31(11): 1754-1766 (2012)

manage site settings

To protect your privacy, all features that rely on external API calls from your browser are turned off by default. You need to opt-in for them to become active. All settings here will be stored as cookies with your web browser. For more information see our F.A.Q.