"A CAD methodology for optimizing transistor current and sizing in analog ..."

David M. Binkley et al. (2003)

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DOI: 10.1109/TCAD.2002.806606

access: closed

type: Journal Article

metadata version: 2020-09-24

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David M. Binkley, C. E. Hopper, Steve D. Tucker, Brian C. Moss, James M. Rochelle, Daniel Foty:
A CAD methodology for optimizing transistor current and sizing in analog CMOS design. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 22(2): 225-237 (2003)

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