"Transistency Models: Memory Ordering at the Hardware-OS Interface."

Daniel Lustig et al. (2017)

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DOI: 10.1109/MM.2017.69

access: closed

type: Journal Article

metadata version: 2017-06-29

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  - https://dblp.org/rec/journals/micro/LustigSBM17
Daniel Lustig, Geet Sethi, Abhishek Bhattacharjee, Margaret Martonosi:
Transistency Models: Memory Ordering at the Hardware-OS Interface. IEEE Micro 37(3): 88-97 (2017)

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