default search action
"A Sub-50-fsrms Jitter Fractional-N CPPLL Based on a ..."
Zonglin Ye et al. (2024)
- Zonglin Ye, Xinlin Geng, Yao Xiao, Qian Xie, Zheng Wang:
A Sub-50-fsrms Jitter Fractional-N CPPLL Based on a Dual-DTC-Assisted Time-Amplifying Phase-Frequency Detector With Cascadable DTC Nonlinearity Compensation Algorithm. IEEE J. Solid State Circuits 59(3): 677-689 (2024)
manage site settings
To protect your privacy, all features that rely on external API calls from your browser are turned off by default. You need to opt-in for them to become active. All settings here will be stored as cookies with your web browser. For more information see our F.A.Q.