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ORCIDQian Xie 0002
Person information
- affiliation: University of Electronic Science and Technology of China, School of Integrated Circuit Science and Engineering, Chengdu, China
- affiliation: University of California, San Diego, CA, USA
- affiliation (PhD 2013): Tsinghua University, Beijing, China
Other persons with the same name
- Qian Xie — disambiguation page
- Qian Xie 0001
![[0000-0001-9901-0396]](https://dblp.uni-trier.de./img/orcid-mark.12x12.png "0000-0001-9901-0396")
— University of Oxford, Department of Computer Science, Oxford, UK (and 1 more) - Qian Xie 0003 — Florida State University, Department of Statistics, Tallahassee, FL, USA
- Qian Xie 0004 — Z-Tech Corporation, National Center for Toxicological Research, and Division of Bioinformatics, Jefferson, AR, USA
- Qian Xie 0005 — Cornell University, School of Operations Research and Information Engineering, Ithaca, NY, USA (and 1 more)
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2020 – today
- 2024
[j10]Zonglin Ye, Xinlin Geng, Yao Xiao, Qian Xie, Zheng Wang:
A Sub-50-fsrms Jitter Fractional-N CPPLL Based on a Dual-DTC-Assisted Time-Amplifying Phase-Frequency Detector With Cascadable DTC Nonlinearity Compensation Algorithm. IEEE J. Solid State Circuits 59(3): 677-689 (2024)- [j9]Fei He, Qian Xie, Zheng Wang:
Analysis and Design of a Novel Gain-Boosting Technique Based on Lossy Series Embedding Network for Near-fmax Embedded Amplifier. IEEE Trans. Circuits Syst. I Regul. Pap. 71(2): 874-884 (2024) - [c12]Zonglin Ye, Xinlin Geng, Zhixiang Shi, Hongyang Zhang, Qian Xie, Zheng Wang:
A 6.8-to-14.4GHz Octave-Tuning Fractional-N Charge-Pump PLL with Slide-Dithering-Based Background DTC Nonlinearity Calibration for Near-Integer Fractional Spur Mitigation Achieving 78fs RMS Jitter and -258.6dB $\text{FoM}_{\mathrm{T}}$. CICC 2024: 1-2 - 2023
- [j8]Zhongchen Xu, Menghu Ni, Qian Xie, Zheng Wang:
Collaborative gain and noise optimization: a design of 150-173-GHz cascode LNA with 22.3 dB gain and 6.92 dB NF based on the gain-noise plane. Sci. China Inf. Sci. 66(10) (2023) - [j7]Fei He, Qian Xie, Zheng Wang:
A novel gain-boosting structure with Z-embedding and parallel pre-embedding network for amplifiers at near-fmax frequencies. Int. J. Circuit Theory Appl. 51(10): 4465-4476 (2023) - [j6]Zhenyi Zhang, Maoxuan Yang, Xinlin Geng, Kailei Wang, Qian Xie, Zheng Wang:
A 0.0325-mm² 114-to-147-GHz 6-Bit Passive Vector-Modulated Phase Shifter With MN-Embedded Isolated Power Combiner Achieving <3.7° RMS Phase Error in 65-nm CMOS. IEEE Trans. Circuits Syst. I Regul. Pap. 70(11): 4394-4405 (2023) - [j5]Zhongchen Xu, Qian Xie, Zheng Wang:
A Study of Collaborative Gain/Noise Optimization for LNAs at Near- Frequencies Based on a Novel Gain-Noise Plane Approach. IEEE Trans. Circuits Syst. II Express Briefs 70(1): 51-55 (2023) - [c11]Xinlin Geng, Zonglin Ye, Yao Xiao, Qian Xie, Zheng Wang:
A 26GHz Fractional-N Charge-Pump PLL Based on A Dual-DTC-Assisted Time-Amplifying-Phase-Frequency Detector Achieving 37.1fs and 45.6fs rms Jitter for Integer-N and Fractional-N Channels. CICC 2023: 1-2 - [c10]Xinlin Geng, Zonglin Ye, Kailei Wang, Hongyang Zhang, Qian Xie, Zheng Wang:
A Compact Frequency Servo SoC with Background Output Power Calibration for Miniaturized Atomic Clocks. ICTA 2023: 1-2 - 2022
- [c9]Wenbo Li, Qian Xie, Zheng Wang:
An Analytical Model for doping effect in charge-plasma-based TFET. ICTA 2022: 186-187 - [c8]Xinlin Geng, Yibo Tian, Yao Xiao, Zonglin Ye, Qian Xie, Zheng Wang:
A 25.8GHz Integer-N PLL With Time-Amplifying Phase-Frequency Detector Achieving 60fsrms Jitter, -252.8dB FoMJ, and Robust Lock Acquisition Performance. ISSCC 2022: 388-390 - 2021
- [j4]Fei He, Qian Xie, Zheng Wang:
A study on gain boosting techniques of cascode amplifier at near-fmax frequencies based on gain plane approach. Microelectron. J. 112: 105064 (2021) - [j3]Xinlin Geng, Qian Xie, Zheng Wang:
A Quadrature Sub-Sampling Phase Detector for Fast-Relocked Sub-Sampling PLL Under External Interference. IEEE Trans. Circuits Syst. II Express Briefs 68(1): 87-91 (2021) - [j2]Fei He, Qian Xie, Zheng Wang:
Optimize the Efficiency of Lossy Matching Network: A Top-Down Splitting Algorithm Based on Generalized Quality-Based Equation. IEEE Trans. Circuits Syst. II Express Briefs 68(8): 2750-2754 (2021) - [c7]Zhenyi Zhang, Qian Xie, Zheng Wang:
A 150-170GHz 5-Bit Vector-Modulated Phase Shifter Based on X-type Phase Inverter Technique. ICTA 2021: 22-23 - [c6]Zixuan Yang, Qian Xie, Qiao He, Meng Zhao, Zheng Wang:
A New Method to Extract Mobility Degradation and Parasitic Series Resistance of Nano-scaled MOSFETs. ICTA 2021: 99-100 - [c5]Meng Zhao, Qian Xie, Zixuan Yang, Qiao He, Zheng Wang:
An Accurate Analytical Model for Small Signal Behavior of MOSFET in Terahertz Applications. ICTA 2021: 107-108 - [c4]Qiao He, Qian Xie, Meng Zhao, Zixuan Yang, Zheng Wang:
An Analytical Model of Energy Band Considering Drain Doping Effect of TFET With Exponential Barrier. ICTA 2021: 109-110 - 2020
- [c3]Menghu Ni, Qian Xie, Fei He, Zheng Wang:
A Novel Design of Double Gain Boosting Inductor Cascode Amplifier at Near-fmax Frequencies. ICTA 2020: 21-22
2010 – 2019
- 2019
- [j1]Qian Xie, Chen Chen, Mingjun Liu, Shuang Xia, Zheng Wang:
Short-channel effects on the static noise margin of 6T SRAM composed of 2D semiconductor MOSFETs. Sci. China Inf. Sci. 62(6): 62404:1-62404:8 (2019) - [c2]Xinlin Geng, Qian Xie, Yibo Tian, Yu Duan, Zheng Wang:
The Design of a 28GHz Mixer-Embedded Frequency Shifting PLL in 65nm CMOS with Low In-Band Phase Noise. ISCAS 2019: 1-4 - [c1]Mingjun Liu, Qian Xie, Shuang Xia, Zheng Wang:
A Novel Step-shaped Gate Tunnel FET with Low Ambipolar Current. ISDCS 2019: 1-4
Coauthor Index
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