"A 3.8-ns CMOS 16*16-b multiplier using complementary pass-transistor logic."

Kazuo Yano et al. (1990)

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DOI: 10.1109/4.52161

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type: Journal Article

metadata version: 2025-01-23

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Kazuo Yano, Toshiaki Yamanaka, Takashi Nishida, Masayoshi Saito, Katsuhiro Shimohigashi, Akihiro Shimizu:
A 3.8-ns CMOS 16*16-b multiplier using complementary pass-transistor logic. IEEE J. Solid State Circuits 25(2): 388-395 (1990)

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