"Design and Implementation of a Hybrid, ADC/DAC-Free, Input-Sparsity-Aware, ..."

Junjie Wang et al. (2024)

> Home

Details and statistics

DOI: 10.1109/JSSC.2023.3304174

access: closed

type: Journal Article

metadata version: 2024-11-15

- view
  - electronic edition via DOI
  - unpaywalled version
  authority control:
- export record
  dblp key:
  - journals/jssc/WangZLLWHCLYH24
- ask others
- share record
  persistent URL:
  - https://dblp.org/rec/journals/jssc/WangZLLWHCLYH24
Junjie Wang, Teng Zhang, Shuang Liu, Yihe Liu, Yuancong Wu, Shaogang Hu, Tupei Chen, Yang Liu, Yuchao Yang, Ru Huang:
Design and Implementation of a Hybrid, ADC/DAC-Free, Input-Sparsity-Aware, Precision Reconfigurable RRAM Processing-in-Memory Chip. IEEE J. Solid State Circuits 59(2): 595-604 (2024)

manage site settings

To protect your privacy, all features that rely on external API calls from your browser are turned off by default. You need to opt-in for them to become active. All settings here will be stored as cookies with your web browser. For more information see our F.A.Q.