"An optimized 1.0- mu m CMOS technology for next-generation channelless ..."

Yukihiro Ushiku et al. (1988)

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DOI: 10.1109/4.1014

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type: Journal Article

metadata version: 2024-11-05

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Yukihiro Ushiku, Teruo Kobayashi, Akito Yoshida, Nobuyuki Itoh, Akira Nishiyama, Rempei Nakata:
An optimized 1.0- mu m CMOS technology for next-generation channelless gate arrays. IEEE J. Solid State Circuits 23(2): 507-513 (1988)

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