"A low-power four-transistor SRAM cell with a stacked vertical poly-silicon ..."

Akira Kotabe et al. (2005)

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DOI: 10.1109/JSSC.2005.845553

access: closed

type: Journal Article

metadata version: 2022-03-02

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Akira Kotabe, Kenichi Osada, Naoki Kitai, Mio Fujioka, Shiro Kamohara, Masahiro Moniwa, Sadayuki Morita, Yoshikazu Saitoh:
A low-power four-transistor SRAM cell with a stacked vertical poly-silicon PMOS and a dual-word-voltage scheme. IEEE J. Solid State Circuits 40(4): 870-876 (2005)

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