"0.13-μm 32-Mb/64-Mb embedded DRAM core with high efficient redundancy ..."

Hirohito Kikukawa et al. (2002)

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DOI: 10.1109/JSSC.2002.1015693

access: closed

type: Journal Article

metadata version: 2022-04-09

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Hirohito Kikukawa, Shigeki Tomishima, Takaharu Tsuji, Toshiaki Kawasaki, Shouji Sakamoto, Masatoshi Ishikawa, Wataru Abe, Hiroaki Tanizaki, Hiroshi Kato, Toshitaka Uchikoba, Toshihiro Inokuchi, Manabu Senoh, Yoshifumi Fukushima, Mitsutaka Niiro, Masanao Maruta, Akinori Shibayama, Tsukasa Ooishi, Kazunari Takahashi, Hideto Hidaka:
0.13-μm 32-Mb/64-Mb embedded DRAM core with high efficient redundancy and enhanced testability. IEEE J. Solid State Circuits 37(7): 932-940 (2002)

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