"A 60-MS/s 5-MHz BW Noise-Shaping SAR ADC With Integrated Input Buffer ..."

Yuekang Guo et al. (2023)

> Home

Details and statistics

DOI: 10.1109/JSSC.2022.3185501

access: closed

type: Journal Article

metadata version: 2023-02-10

- view
  - electronic edition via DOI
  - unpaywalled version
  authority control:
- export record
  dblp key:
  - journals/jssc/GuoJLZ23
- ask others
- share record
  persistent URL:
  - https://dblp.org/rec/journals/jssc/GuoJLZ23
Yuekang Guo, Jing Jin, Xiaoming Liu, Jianjun Zhou:
A 60-MS/s 5-MHz BW Noise-Shaping SAR ADC With Integrated Input Buffer Achieving 84.2-dB SNDR and 97.3-dB SFDR Using Dynamic Level-Shifting and ISI-Error Correction. IEEE J. Solid State Circuits 58(2): 474-485 (2023)

manage site settings

To protect your privacy, all features that rely on external API calls from your browser are turned off by default. You need to opt-in for them to become active. All settings here will be stored as cookies with your web browser. For more information see our F.A.Q.