"A 500-MHz multi-banked compilable DRAM macro with direct write and ..."

John E. Barth Jr. et al. (2005)

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DOI: 10.1109/JSSC.2004.838001

access: closed

type: Journal Article

metadata version: 2022-04-09

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John E. Barth Jr., Darren Anand, Steve Burns, Jeffrey H. Dreibelbis, John A. Fifield, Kevin W. Gorman, Michael R. Nelms, Erik Nelson, Adrian Paparelli, Gary Pomichter, Dale E. Pontius, Stephen Sliva:
A 500-MHz multi-banked compilable DRAM macro with direct write and programmable pipelining. IEEE J. Solid State Circuits 40(1): 213-222 (2005)

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