"An experimental 1-Mbit cache DRAM with ECC."

Mikio Asakura et al. (1990)

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DOI: 10.1109/4.50276

access: closed

type: Journal Article

metadata version: 2025-01-23

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Mikio Asakura, Yoshio Matsuda, Hidaka Hidaka, Yoshinori Tanaka, Kazuyasu Fujishima:
An experimental 1-Mbit cache DRAM with ECC. IEEE J. Solid State Circuits 25(1): 5-10 (1990)

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