"High-Speed Power Allocation in NOMA System Using FPGA-Based DNN."

Rama Muni Reddy Yanamala, Muralidhar Pullakandam (2024)

> Home

Details and statistics

DOI: 10.1142/S0218126624200044

access: closed

type: Journal Article

metadata version: 2024-09-20

- view
  - electronic edition via DOI
  - unpaywalled version
  authority control:
- export record
  dblp key:
  - journals/jcsc/YanamalaP24
- ask others
- share record
  persistent URL:
  - https://dblp.org/rec/journals/jcsc/YanamalaP24
Rama Muni Reddy Yanamala, Muralidhar Pullakandam:
High-Speed Power Allocation in NOMA System Using FPGA-Based DNN. J. Circuits Syst. Comput. 33(14): 2420004:1-2420004:13 (2024)

manage site settings

To protect your privacy, all features that rely on external API calls from your browser are turned off by default. You need to opt-in for them to become active. All settings here will be stored as cookies with your web browser. For more information see our F.A.Q.