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ORCIDMuralidhar Pullakandam
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2020 – today
- 2025
[j6]Rama Muni Reddy Yanamala, Muralidhar Pullakandam:
FPGA-accelerated hybrid CNN-LSTM system for efficient EEG-based drowsiness recognition. J. Supercomput. 81(3): 453 (2025)- 2024
- [j5]Rama Muni Reddy Yanamala
, Muralidhar Pullakandam:
Empowering edge devices: FPGA-based 16-bit fixed-point accelerator with SVD for CNN on 32-bit memory-limited systems. Int. J. Circuit Theory Appl. 52(9): 4755-4782 (2024) - [j4]Rama Muni Reddy Yanamala, Muralidhar Pullakandam:
High-Speed Power Allocation in NOMA System Using FPGA-Based DNN. J. Circuits Syst. Comput. 33(14): 2420004:1-2420004:13 (2024) - 2023
- [j3]Rama Muni Reddy Yanamala, Muralidhar Pullakandam:
A high-speed reusable quantized hardware accelerator design for CNN on constrained edge device. Des. Autom. Embed. Syst. 27(3): 165-189 (2023) - [j2]B. B. Shabarinath, Muralidhar Pullakandam:
SoC-based real-time SVM classification with integrated training using HLS and PYNQ. Microprocess. Microsystems 101: 104878 (2023) - [c6]Roshan Agarwal, Muralidhar Pullakandam, Gopinath Agrahara, Amarnadh Akavarapu:
Advanced Powerplanning Strategy Utilising Aprisa - Image Edge Detector. ICCCNT 2023: 1-5 - [c5]Sujay Kumar Mandal, Muralidhar Pullakandam, Rama Muni Reddy Yanamala:
Pneumonia Detection Using Transfer Learning And Hardware Implementation in Edge TPU. ICCCNT 2023: 1-5 - 2022
- [c4]Rama Muni Reddy Yanamala, Muralidhar Pullakandam:
An Efficient Configurable Hardware Accelerator Design for CNN on Low Memory 32-Bit Edge Device. iSES 2022: 112-117 - [c3]Raveendra Podeti, Sreehari Rao Patri, Muralidhar Pullakandam:
The chaotic-based challenge feed mechanism for Arbiter Physical Unclonable Functions (APUFs) with enhanced reliability in IoT security. iSES 2022: 118-123 - [c2]Nandini Jali, Muralidhar Pullakandam, Sreehari Rao Patri:
Efficient successive cancellation decoder architecture for multi-kernel polar codes. iSES 2022: 248-250 - 2021
- [j1]Raveendra Podeti, Sreehari Rao Patri, Muralidhar Pullakandam:
Highly reliable XoR Feed Arbiter Physical Unclonable Function (XFAPUF) in 180 nm process for IoT security. Microprocess. Microsystems 87: 104355 (2021) - [c1]Raveendra Podeti, Srihari Rao Patri, Srinivas Katkoori, Muralidhar Pullakandam:
ReOPUF: Relaxation Oscillator Physical Unclonable Function for Reliable Key Generation in IoT Security. IFIPIoT 2021: 163-179
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