"A formal model for proving hardware timing properties and identifying ..."

Maoyuan Qin et al. (2020)

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DOI: 10.1016/J.VLSI.2020.02.001

access: closed

type: Journal Article

metadata version: 2020-03-24

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Maoyuan Qin, Xinmu Wang, Baolei Mao, Dejun Mu, Wei Hu:
A formal model for proving hardware timing properties and identifying timing channels. Integr. 72: 123-133 (2020)

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