"Efficient hardware architecture for integer implementation of ..."

S. D. Jayavathi, A. Shenbagavalli, B. Ganapathy Ram (2018)

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DOI: 10.1504/IJBIDM.2017.10004685

access: closed

type: Journal Article

metadata version: 2020-07-30

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S. D. Jayavathi, A. Shenbagavalli, B. Ganapathy Ram:
Efficient hardware architecture for integer implementation of multi-alphabet arithmetic coding for data mining. Int. J. Bus. Intell. Data Min. 13(1/2/3): 188-208 (2018)

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