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S. D. Jayavathi

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2010 – 2019

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2019
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S. D. Jayavathi, A. Shenbagavalli:
FPGA-based Auxiliary Minutest MQ-coder architecture of JPEG2000. J. Real Time Image Process. 16(5): 1765-1779 (2019)
2018
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S. D. Jayavathi, A. Shenbagavalli, B. Ganapathy Ram:
Efficient hardware architecture for integer implementation of multi-alphabet arithmetic coding for data mining. Int. J. Bus. Intell. Data Min. 13(1/2/3): 188-208 (2018)

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