"A data-aware write-assist 10T SRAM cell with bit-interleaving capability."

Shivram Mansore, Radheshyam Gamad (2018)

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DOI: 10.3906/ELK-1801-272

access: open

type: Journal Article

metadata version: 2021-06-04

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Shivram Mansore, Radheshyam Gamad:
A data-aware write-assist 10T SRAM cell with bit-interleaving capability. Turkish J. Electr. Eng. Comput. Sci. 26(5): 2361-2373 (2018)

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