"Single-Stage Vernier Time-to-Digital Converter with Sub-Gate Delay Time ..."

Chin-Hsin Lin, Marek Syrzycki (2011)

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DOI: 10.4236/CS.2011.24050

access: open

type: Journal Article

metadata version: 2020-06-08

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Chin-Hsin Lin, Marek Syrzycki:
Single-Stage Vernier Time-to-Digital Converter with Sub-Gate Delay Time Resolution. Circuits Syst. 2(4): 365-371 (2011)

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