"Co-design of a novel CMOS highly parallel, low-power, multi-chip neural ..."

Wolfgang Hokenmaier et al. (2024)

> Home

Details and statistics

DOI: 10.48550/ARXIV.2409.19389

access: open

type: Informal or Other Publication

metadata version: 2024-10-17

- view
  - electronic edition via DOI (open access)
  authority control:
- export record
  dblp key:
  - journals/corr/abs-2409-19389
- ask others
- share record
  persistent URL:
  - https://dblp.org/rec/journals/corr/abs-2409-19389
Wolfgang Hokenmaier, Ryan Jurasek, Elijah F. W. Bowen, R. Granger, D. Odom:
Co-design of a novel CMOS highly parallel, low-power, multi-chip neural network accelerator. CoRR abs/2409.19389 (2024)

manage site settings

To protect your privacy, all features that rely on external API calls from your browser are turned off by default. You need to opt-in for them to become active. All settings here will be stored as cookies with your web browser. For more information see our F.A.Q.