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2020 – today
- 2024
[i1]Wolfgang Hokenmaier, Ryan Jurasek, Elijah F. W. Bowen, R. Granger, D. Odom:
Co-design of a novel CMOS highly parallel, low-power, multi-chip neural network accelerator. CoRR abs/2409.19389 (2024)- 2020
- [c2]Marcia Golmohamadi, Ryan Jurasek, Wolfgang Hokenmaier, Donald Labrecque, Ruoyu Zhi, Bret Dale, Nibir Islam, Dave Kinney, Angela Johnson:
Verification and Testing Considerations of an In-Memory AI Chip. NATW 2020: 1-6
2010 – 2019
- 2018
- [c1]Ryan Pennucci, Ryan Jurasek, Wolfgang Hokenmaier, Lester Patrick, Jacob Bucci, Donald Labrecque, David Kinney:
An analysis of an inexpensive memory test solution. NATW 2018: 1-6
2000 – 2009
- 2005
- [j1]Joseph T. Kennedy, Randy Mooney, Robert Ellis, James E. Jaussi, Shekhar Borkar, Jung-Hwan Choi, Jae-Kwan Kim, Chan-Kyong Kim, Woo-Seop Kim, Chang-Hyun Kim, Soo-In Cho, Steffen Loeffler, Jochen Hoffmann, Wolfgang Hokenmaier, Russ Houghton, Thomas Vogelsang
:
A 3.6-Gb/s point-to-point heterogeneous-voltage-capable DRAM interface for capacity-scalable memory subsystems. IEEE J. Solid State Circuits 40(1): 233-244 (2005)
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last updated on 2024-10-18 20:29 CEST by the dblp team
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