"Low-Latency VLSI Architectures for Modular Polynomial Multiplication via ..."

Weihang Tan et al. (2021)

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DOI: —

access: open

type: Informal or Other Publication

metadata version: 2021-10-28

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  - electronic edition @ arxiv.org (open access)
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  - journals/corr/abs-2110-12127
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  - https://dblp.org/rec/journals/corr/abs-2110-12127
Weihang Tan, Antian Wang, Yingjie Lao, Xinmiao Zhang, Keshab K. Parhi:
Low-Latency VLSI Architectures for Modular Polynomial Multiplication via Fast Filtering and Applications to Lattice-Based Cryptography. CoRR abs/2110.12127 (2021)

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