"Logic Design for On-Chip Test Clock Generation - Implementation Details ..."

Matthias Beck et al. (2007)

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DOI: —

access: open

type: Informal or Other Publication

metadata version: 2018-08-13

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  - electronic edition @ arxiv.org (open access)
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  dblp key:
  - journals/corr/abs-0710-4763
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  - https://dblp.org/rec/journals/corr/abs-0710-4763
Matthias Beck, Olivier Barondeau, Martin Kaibel, Frank Poehl, Xijiang Lin, Ron Press:
Logic Design for On-Chip Test Clock Generation - Implementation Details and Impact on Delay Test Quality. CoRR abs/0710.4763 (2007)

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