"A Design and Yield Evaluation Technique for Wafer-Scale Memory."

Koichi Yamashita, Shohei Ikehara (1992)

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DOI: 10.1109/2.129042

access: closed

type: Journal Article

metadata version: 2020-08-12

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  - https://dblp.org/rec/journals/computer/YamashitaI92
Koichi Yamashita, Shohei Ikehara:
A Design and Yield Evaluation Technique for Wafer-Scale Memory. Computer 25(4): 19-27 (1992)

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