"A 50 MS/s 65 dB-SNDR Pipelined SAR ADC using Capacitively Degenerated ..."

Hyunchul Yoon et al. (2022)

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DOI: 10.1109/VLSITECHNOLOGYANDCIR46769.2022.9830300

access: closed

type: Conference or Workshop Paper

metadata version: 2022-08-04

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Hyunchul Yoon, Teawoong Kim, Yigi Kwon, Youngcheol Chae:
A 50 MS/s 65 dB-SNDR Pipelined SAR ADC using Capacitively Degenerated Two-Stage Dynamic Amplifier. VLSI Technology and Circuits 2022: 88-89

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