"A Test Generator for Segment Delay Faults."

Keerthi Heragu, Janak H. Patel, Vishwani D. Agrawal (1999)

> Home

Details and statistics

DOI: 10.1109/ICVD.1999.745202

access: closed

type: Conference or Workshop Paper

metadata version: 2023-03-24

- view
  authority control:
- export record
  dblp key:
  - conf/vlsid/HeraguPA99
- ask others
- share record
  persistent URL:
  - https://dblp.org/rec/conf/vlsid/HeraguPA99
Keerthi Heragu, Janak H. Patel, Vishwani D. Agrawal:
A Test Generator for Segment Delay Faults. VLSI Design 1999: 484-491

manage site settings

To protect your privacy, all features that rely on external API calls from your browser are turned off by default. You need to opt-in for them to become active. All settings here will be stored as cookies with your web browser. For more information see our F.A.Q.