"Vertical Nanowire FET Based Standard Cell Design Employing Verilog-A ..."

Satish Maheshwaram et al. (2017)

> Home

Details and statistics

DOI: 10.1007/978-981-10-7470-7_24

access: closed

type: Conference or Workshop Paper

metadata version: 2023-08-17

- view
  - electronic edition via DOI
  - unpaywalled version
  authority control:
- export record
  dblp key:
  - conf/vdat/MaheshwaramPSBM17
- ask others
- share record
  persistent URL:
  - https://dblp.org/rec/conf/vdat/MaheshwaramPSBM17
Satish Maheshwaram, Om. Prakash, Mohit Sharma, Anand Bulusu, Sanjeev Manhas:
Vertical Nanowire FET Based Standard Cell Design Employing Verilog-A Compact Model for Higher Performance. VDAT 2017: 239-248

manage site settings

To protect your privacy, all features that rely on external API calls from your browser are turned off by default. You need to opt-in for them to become active. All settings here will be stored as cookies with your web browser. For more information see our F.A.Q.