"Efficient scalable hardware architecture for highly performant encoded ..."

Hugues Wouafo et al. (2017)

> Home

Details and statistics

DOI: 10.1109/SIPS.2017.8109986

access: closed

type: Conference or Workshop Paper

metadata version: 2017-11-29

- view
  - electronic edition via DOI
  - unpaywalled version
  authority control:
- export record
  dblp key:
  - conf/sips/WouafoCCD17
- ask others
- share record
  persistent URL:
  - https://dblp.org/rec/conf/sips/WouafoCCD17
Hugues Wouafo, Cyrille Chavet, Philippe Coussy, Robin Danilo:
Efficient scalable hardware architecture for highly performant encoded neural networks. SiPS 2017: 1-6

manage site settings

To protect your privacy, all features that rely on external API calls from your browser are turned off by default. You need to opt-in for them to become active. All settings here will be stored as cookies with your web browser. For more information see our F.A.Q.