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"UVM-Based Verification of a Mixed-Signal Design Using SystemVerilog."
Nikolaos Georgoulopoulos, Ioannis Giannou, Alkiviadis A. Hatzopoulos (2018)
- Nikolaos Georgoulopoulos, Ioannis Giannou, Alkiviadis A. Hatzopoulos:
UVM-Based Verification of a Mixed-Signal Design Using SystemVerilog. PATMOS 2018: 97-102
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