"A Fault Modeling Technique to Test Memory BIST Algorithms."

Raja Venkatesh et al. (2002)

> Home

Details and statistics

DOI: 10.1109/MTDT.2002.1029771

access: closed

type: Conference or Workshop Paper

metadata version: 2023-03-24

- view
  authority control:
- export record
  dblp key:
  - conf/mtdt/VenkateshKPS02
- ask others
- share record
  persistent URL:
  - https://dblp.org/rec/conf/mtdt/VenkateshKPS02
Raja Venkatesh, Sailesh Kumar, Joji Philip, Sunil Shukla:
A Fault Modeling Technique to Test Memory BIST Algorithms. MTDT 2002: 109-116

manage site settings

To protect your privacy, all features that rely on external API calls from your browser are turned off by default. You need to opt-in for them to become active. All settings here will be stored as cookies with your web browser. For more information see our F.A.Q.