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2020 – today
- 2023
[c28]Tim C. Fischer, Anantha Kumar Nivarti, Raghuvir Ramachandran, Ram Bharti, Derek Carson, Anton Lawrendra, Vineet Mudgal, Vivek Santhosh, Sunil Shukla, Te-Chen Tsai:
D1: A 7nm ML Training Processor with Wave Clock Distribution. ISSCC 2023: 156-157- [c27]Ankur Agrawal, Monodeep Kar, Kyu-Hyoun Kim
, Sergey V. Rylov, Jinwook Jung, Seiji Munetoh, Kohji Hosokawa, Xin Zhang, Bahman Hekmatshoartabari, Fabio Carta, Martin Cochet, Robert Casatuta, Mingu Kang, Sunil Shukla, Kailash Gopalakrishnan, Leland Chang:
A Switched-Capacitor Integer Compute Unit with Decoupled Storage and Arithmetic for Cloud AI Inference in 5nm CMOS. VLSI Technology and Circuits 2023: 1-2 - 2022
- [j6]Sae Kyu Lee, Ankur Agrawal, Joel Silberman, Matthew M. Ziegler, Mingu Kang, Swagath Venkataramani, Nianzheng Cao, Bruce M. Fleischer, Michael Guillorn, Matthew Cohen, Silvia M. Mueller, Jinwook Oh, Martin Lutz, Jinwook Jung, Siyu Koswatta, Ching Zhou, Vidhi Zalani, Monodeep Kar, James Bonanno, Robert Casatuta, Chia-Yu Chen, Jungwook Choi, Howard Haynie, Alyssa Herbert, Radhika Jain, Kyu-Hyoun Kim, Yulong Li, Zhibin Ren, Scot Rider, Marcel Schaal, Kerstin Schelm, Michael Scheuermann, Xiao Sun, Hung Tran, Naigang Wang, Wei Wang, Xin Zhang, Vinay Shah, Brian W. Curran, Vijayalakshmi Srinivasan, Pong-Fei Lu, Sunil Shukla, Kailash Gopalakrishnan, Leland Chang:
A 7-nm Four-Core Mixed-Precision AI Chip With 26.2-TFLOPS Hybrid-FP8 Training, 104.9-TOPS INT4 Inference, and Workload-Aware Throttling. IEEE J. Solid State Circuits 57(1): 182-197 (2022) - [c26]Sukhdeep Kaur, Kapil Joshi, Mudduluru Charan Teja, Ajay Singh, Amen A. Khabeer, Sunil Shukla:
Sensor based Smart Plant Monitoring using IOT and Deep Learning: A Systematic Approach. ICCCS 2022: 1-4 - 2021
- [c25]Swagath Venkataramani, Vijayalakshmi Srinivasan, Wei Wang, Sanchari Sen, Jintao Zhang, Ankur Agrawal, Monodeep Kar, Shubham Jain, Alberto Mannari, Hoang Tran, Yulong Li, Eri Ogawa, Kazuaki Ishizaki, Hiroshi Inoue, Marcel Schaal, Mauricio J. Serrano, Jungwook Choi, Xiao Sun, Naigang Wang, Chia-Yu Chen, Allison Allain, James Bonanno, Nianzheng Cao, Robert Casatuta, Matthew Cohen, Bruce M. Fleischer, Michael Guillorn, Howard Haynie, Jinwook Jung, Mingu Kang, Kyu-Hyoun Kim, Siyu Koswatta, Sae Kyu Lee, Martin Lutz, Silvia M. Mueller, Jinwook Oh, Ashish Ranjan, Zhibin Ren, Scot Rider, Kerstin Schelm, Michael Scheuermann, Joel Silberman, Jie Yang, Vidhi Zalani, Xin Zhang, Ching Zhou, Matthew M. Ziegler, Vinay Shah, Moriyoshi Ohara, Pong-Fei Lu, Brian W. Curran, Sunil Shukla, Leland Chang, Kailash Gopalakrishnan:
RaPiD: AI Accelerator for Ultra-low Precision Training and Inference. ISCA 2021: 153-166 - [c24]Ankur Agrawal, Sae Kyu Lee, Joel Silberman, Matthew M. Ziegler, Mingu Kang, Swagath Venkataramani, Nianzheng Cao, Bruce M. Fleischer, Michael Guillorn, Matt Cohen, Silvia M. Mueller, Jinwook Oh, Martin Lutz, Jinwook Jung, Siyu Koswatta, Ching Zhou, Vidhi Zalani, James Bonanno, Robert Casatuta, Chia-Yu Chen, Jungwook Choi, Howard Haynie, Alyssa Herbert, Radhika Jain, Monodeep Kar, Kyu-Hyoun Kim, Yulong Li, Zhibin Ren, Scot Rider, Marcel Schaal, Kerstin Schelm, Michael Scheuermann, Xiao Sun, Hung Tran, Naigang Wang, Wei Wang, Xin Zhang, Vinay Shah, Brian W. Curran, Vijayalakshmi Srinivasan, Pong-Fei Lu, Sunil Shukla, Leland Chang, Kailash Gopalakrishnan:
A 7nm 4-Core AI Chip with 25.6TFLOPS Hybrid FP8 Training, 102.4TOPS INT4 Inference and Workload-Aware Throttling. ISSCC 2021: 144-146 - 2020
- [j5]Swagath Venkataramani, Xiao Sun, Naigang Wang, Chia-Yu Chen, Jungwook Choi, Mingu Kang, Ankur Agarwal, Jinwook Oh, Shubham Jain, Tina Babinsky, Nianzheng Cao, Thomas W. Fox, Bruce M. Fleischer, George Gristede, Michael Guillorn, Howard Haynie, Hiroshi Inoue, Kazuaki Ishizaki, Michael J. Klaiber, Shih-Hsien Lo, Gary W. Maier, Silvia M. Mueller, Michael Scheuermann, Eri Ogawa, Marcel Schaal, Mauricio J. Serrano, Joel Silberman, Christos Vezyrtzis, Wei Wang, Fanchieh Yee, Jintao Zhang, Matthew M. Ziegler, Ching Zhou, Moriyoshi Ohara, Pong-Fei Lu, Brian W. Curran, Sunil Shukla, Vijayalakshmi Srinivasan, Leland Chang, Kailash Gopalakrishnan:
Efficient AI System Design With Cross-Layer Approximate Computing. Proc. IEEE 108(12): 2232-2250 (2020) - [c23]Jinwook Oh, Sae Kyu Lee, Mingu Kang, Matthew M. Ziegler, Joel Silberman, Ankur Agrawal, Swagath Venkataramani, Bruce M. Fleischer, Michael Guillorn, Jungwook Choi, Wei Wang, Silvia M. Mueller, Shimon Ben-Yehuda, James Bonanno, Nianzheng Cao, Robert Casatuta, Chia-Yu Chen, Matt Cohen, Ophir Erez, Thomas W. Fox, George Gristede, Howard Haynie, Vicktoria Ivanov, Siyu Koswatta, Shih-Hsien Lo, Martin Lutz, Gary W. Maier, Alex Mesh, Yevgeny Nustov, Scot Rider, Marcel Schaal, Michael Scheuermann, Xiao Sun, Naigang Wang, Fanchieh Yee, Ching Zhou, Vinay Shah, Brian W. Curran, Vijayalakshmi Srinivasan, Pong-Fei Lu, Sunil Shukla, Kailash Gopalakrishnan, Leland Chang:
A 3.0 TFLOPS 0.62V Scalable Processor Core for High Compute Utilization AI Training and Inference. VLSI Circuits 2020: 1-2
2010 – 2019
- 2018
- [c22]Vijayalakshmi Srinivasan, Bruce M. Fleischer, Sunil Shukla, Matthew M. Ziegler, Joel Silberman, Jinwook Oh, Jungwook Choi, Silvia M. Mueller, Ankur Agrawal, Tina Babinsky, Nianzheng Cao, Chia-Yu Chen, Pierce Chuang, Thomas W. Fox, George Gristede, Michael Guillorn, Howard Haynie, Michael J. Klaiber, Dongsoo Lee, Shih-Hsien Lo, Gary W. Maier, Michael Scheuermann, Swagath Venkataramani, Christos Vezyrtzis, Naigang Wang, Fanchieh Yee, Ching Zhou, Pong-Fei Lu, Brian W. Curran, Leland Chang, Kailash Gopalakrishnan:
Across the Stack Opportunities for Deep Learning Acceleration. ISLPED 2018: 35:1-35:2 - [c21]Bruce M. Fleischer, Sunil Shukla, Matthew M. Ziegler, Joel Silberman, Jinwook Oh, Vijayalakshmi Srinivasan, Jungwook Choi, Silvia M. Mueller, Ankur Agrawal, Tina Babinsky, Nianzheng Cao, Chia-Yu Chen, Pierce Chuang, Thomas W. Fox, George Gristede, Michael Guillorn, Howard Haynie, Michael J. Klaiber, Dongsoo Lee, Shih-Hsien Lo, Gary W. Maier, Michael Scheuermann, Swagath Venkataramani, Christos Vezyrtzis, Naigang Wang, Fanchieh Yee, Ching Zhou, Pong-Fei Lu, Brian W. Curran, Leland Chang, Kailash Gopalakrishnan:
A Scalable Multi- TeraOPS Deep Learning Processor Core for AI Trainina and Inference. VLSI Circuits 2018: 35-36 - 2017
- [c20]Ankur Agrawal, Chia-Yu Chen, Jungwook Choi, Kailash Gopalakrishnan, Jinwook Oh, Sunil Shukla, Viji Srinivasan, Swagath Venkataramani, Wei Zhang:
Accelerator Design for Deep Learning Training: Extended Abstract: Invited. DAC 2017: 57:1-57:2 - 2016
- [c19]Ankur Agrawal, Jungwook Choi, Kailash Gopalakrishnan, Suyog Gupta, Ravi Nair, Jinwook Oh, Daniel A. Prener, Sunil Shukla, Vijayalakshmi Srinivasan, Zehra Sura:
Approximate computing: Challenges and opportunities. ICRC 2016: 1-8 - 2015
- [c18]Sunil Shukla, David F. Bacon:
Cycle-Accurate Replay and Debugging of Running FPGA Systems. FCCM 2015: 30 - [c17]Joshua S. Auerbach, David F. Bacon, Perry Cheng, Stephen J. Fink, Rodric M. Rabbah, Sunil Shukla:
Growing a Software Language for Hardware Design. SNAPL 2015: 32-40 - 2014
- [c16]David F. Bacon, Perry Cheng, Sunil Shukla:
Parallel real-time garbage collection of multiple heaps in reconfigurable hardware. ISMM 2014: 117-127 - 2013
- [j4]David F. Bacon, Rodric M. Rabbah, Sunil Shukla:
FPGA programming for the masses. Commun. ACM 56(4): 56-63 (2013) - [j3]David F. Bacon, Perry Cheng, Sunil Shukla:
And then there were none: a stall-free real-time garbage collector for reconfigurable hardware. Commun. ACM 56(12): 101-109 (2013) - [j2]David F. Bacon, Rodric M. Rabbah, Sunil Shukla:
FPGA Programming for the Masses. ACM Queue 11(2): 40 (2013) - [j1]Neil W. Bergmann, Sunil Shukla, Jürgen Becker:
QUKU: A dual-layer reconfigurable architecture. ACM Trans. Embed. Comput. Syst. 12(1s): 63:1-63:26 (2013) - [c15]Perry Cheng, Stephen J. Fink, Rodric M. Rabbah, Sunil Shukla:
The Liquid Metal IP bridge. ASP-DAC 2013: 313-319 - 2012
- [c14]Joshua S. Auerbach, David F. Bacon, Ioana Burcea, Perry Cheng, Stephen J. Fink, Rodric M. Rabbah, Sunil Shukla:
A compiler and runtime for heterogeneous computing. DAC 2012: 271-276 - [c13]David F. Bacon, Perry Cheng, Sunil Shukla:
And then there were none: a stall-free real-time garbage collector for reconfigurable hardware. PLDI 2012: 23-34 - 2011
- [c12]Joshua S. Auerbach, David F. Bacon, Perry Cheng, Rodric M. Rabbah, Sunil Shukla:
Virtualization of heterogeneous machines hardware description in a synthesizable object-oriented language. DAC 2011: 890-894 - 2010
- [c11]Sunil Shukla:
Improving intelligibility of synthesized speech in noise with emphasized prosody. ExLing 2010: 161-164 - [c10]Sunil Shukla, Rodric M. Rabbah, Martin Vorbach:
FPGA-based combined architecture for stream categorization and intrusion detection. MEMOCODE 2010: 77-80
2000 – 2009
- 2008
- [b2]Sunil Shukla:
QUKU: A Mixed Grain Dynamically Reconfigurable Architecture for High Performance Computing. University of Queensland, Australia, 2008 - [c9]Sunil Shukla, Neil W. Bergmann, Jürgen Becker:
A Web Server Based Edge Detector Implementation in FPGA. ISVLSI 2008: 441-446 - 2007
- [b1]Sunil Shukla:
Improving High Quality Concatenative Text-to-Speech Using the Circular Linear Prediction Model. Georgia Institute of Technology, Atlanta, GA, USA, 2007 - [c8]Sunil Shukla, Thomas P. Barnwell III:
Improving High Quality TTS using Circular Linear Prediction and Constant Pitch Transform. ICASSP (4) 2007: 681-684 - [c7]Sunil Shukla, Neil W. Bergmann, Jürgen Becker:
QUKU: A FPGA Based Flexible Coarse Grain Architecture Design Paradigm using Process Networks. IPDPS 2007: 1-7 - 2006
- [c6]Sunil Shukla, Neil W. Bergmann, Jürgen Becker:
QUKU: A Fast Run Time Reconfigurable Platform for Image Edge Detection. ARC 2006: 93-98 - [c5]Carlos Morra, M. Sackmann, Sunil Shukla, Jürgen Becker, Reiner W. Hartenstein:
From Equation to VHDL: Using Rewriting Logic for Automated Function Generation. FPL 2006: 1-4 - [c4]Sunil Shukla, Neil W. Bergmann, Jürgen Becker:
QUKU: A Two-Level Reconfigurable Architecture. ISVLSI 2006: 109-116 - [i1]Sunil Shukla, Neil W. Bergmann, Jürgen Becker:
QUKU: A Coarse Grained Paradigm for FPGAs. Dynamically Reconfigurable Architectures 2006 - 2004
- [c3]Sunil Shukla, Neil W. Bergmann:
Single bit error correction implementation in CRC-16 on FPGA. FPT 2004: 319-322 - 2002
- [c2]Sunil Shukla, Ali Erdem Ertan, Thomas P. Barnwell III:
Circular LPC modeling and constant pitch transform for accurate speech analysis and high quality speech synthesis. ICASSP 2002: 269-272 - [c1]Raja Venkatesh, Sailesh Kumar, Joji Philip, Sunil Shukla:
A Fault Modeling Technique to Test Memory BIST Algorithms. MTDT 2002: 109-116
Coauthor Index
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