"NBTI-aware technique for transistor sizing of high-performance CMOS gates."

Maurício Banaszeski da Silva et al. (2009)

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DOI: 10.1109/LATW.2009.4813795

access: closed

type: Conference or Workshop Paper

metadata version: 2023-08-06

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Maurício Banaszeski da Silva, Vinicius V. A. Camargo, Lucas Brusamarello, Gilson I. Wirth, Roberto da Silva:
NBTI-aware technique for transistor sizing of high-performance CMOS gates. LATW 2009: 1-5

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