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ORCIDLucas Brusamarello
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2010 – 2019
- 2012
[j5]Gilson I. Wirth
, Dragica Vasileska, N. Ashraf, Lucas Brusamarello, R. Della Giustina, P. Srinivasan:
Compact modeling and simulation of Random Telegraph Noise under non-stationary conditions in the presence of random dopants. Microelectron. Reliab. 52(12): 2955-2961 (2012)- 2011
- [b1]Lucas Brusamarello:
Modeling and simulation of device variability and reliability at the electrical level. Universidade Federal do Rio Grande do Sul, Porto Alegre, Brazil, 2011 - [j4]Lucas Brusamarello, Gilson I. Wirth, Philippe Roussel, Miguel Miranda:
Fast and accurate statistical characterization of standard cell libraries. Microelectron. Reliab. 51(12): 2341-2350 (2011) - [c5]Miguel Miranda, Philippe Roussel, Lucas Brusamarello, Gilson I. Wirth:
Statistical characterization of standard cells using design of experiments with response surface modeling. DAC 2011: 77-82
2000 – 2009
- 2009
- [j3]Lucas Brusamarello, Gilson I. Wirth, Roberto da Silva:
Statistical RTS model for digital circuits. Microelectron. Reliab. 49(9-11): 1064-1069 (2009) - [c4]Maurício Banaszeski da Silva, Vinicius V. A. Camargo, Lucas Brusamarello, Gilson I. Wirth, Roberto da Silva:
NBTI-aware technique for transistor sizing of high-performance CMOS gates. LATW 2009: 1-5 - 2008
- [j2]Lucas Brusamarello, Roberto da Silva, Gilson I. Wirth, Ricardo A. L. Reis:
Probabilistic Approach for Yield Analysis of Dynamic Logic Circuits. IEEE Trans. Circuits Syst. I Regul. Pap. 55-I(8): 2238-2248 (2008) - 2007
- [j1]Lucas Brusamarello, Roberto da Silva, Gilson I. Wirth, Ricardo Augusto da Luz Reis:
Técnicas probabilísticas para análise de yield em nível elétrico usando propagação de erros e derivadas numéricas. RITA 14(2): 69-89 (2007) - [c3]Lucas Brusamarello, Roberto da Silva, Ricardo A. L. Reis, Gilson I. Wirth:
Yield Analysis by Error Propagation Using Numerical Derivatives Considering WD and D2D variations. ISVLSI 2007: 86-91 - [c2]Lucas Brusamarello, Roberto da Silva, Gilson I. Wirth, Ricardo Reis:
Statistical and Numerical Approach for a Computer efficient circuit yield analysis. VLSI-SoC (Selected Papers) 2007: 1-24 - [c1]Lucas Brusamarello, Roberto da Silva, Gilson I. Wirth, Ricardo A. L. Reis:
Obtaining delay distribution of dynamic logic circuits by error propagation at the electrical level. VLSI-SoC 2007: 94-98
Coauthor Index
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