"Measuring the effectiveness of symmetric and asymmetric transistor sizing ..."

Thiago Assis et al. (2009)

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DOI: 10.1109/LATW.2009.4813789

access: closed

type: Conference or Workshop Paper

metadata version: 2023-08-06

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Thiago Assis, Fernanda Lima Kastensmidt, Gilson I. Wirth, Ricardo Reis:
Measuring the effectiveness of symmetric and asymmetric transistor sizing for Single Event Transient mitigation in CMOS 90nm technologies. LATW 2009: 1-6

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