"Four-Valued Memory Circuit Designed by Multiple-Peak MOS-NDR Devices and ..."

Dong-Shong Liang et al. (2005)

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DOI: 10.1109/IWSOC.2005.66

access: closed

type: Conference or Workshop Paper

metadata version: 2023-03-23

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Dong-Shong Liang, Kwang-Jow Gan, Long-Xian Su, Chi-Pin Chen, Chung-Chih Hsiao, Cher-Shiung Tsai, Yaw-Hwang Chen, Shih-Yu Wang, Shun-Huo Kuo, Feng-Chang Chiang:
Four-Valued Memory Circuit Designed by Multiple-Peak MOS-NDR Devices and Circuits. IWSOC 2005: 78-81

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