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2010 – 2019
- 2013
[j5]Wen-Kuan Yeh, Po-Ying Chen, Kwang-Jow Gan, Jer-Chyi Wang
, Chao-Sung Lai:
The impact of interface/border defect on performance and reliability of high-k/metal-gate CMOSFET. Microelectron. Reliab. 53(2): 265-269 (2013)- 2011
- [j4]Kwang-Jow Gan, Cher-Shiung Tsai, Yu-Kuang Li, Jenq-Jong Lu:
Logic circuit design using monostable-bistable transition logic element based on standard BiCMOS process. Microelectron. J. 42(2): 477-482 (2011) - 2010
- [j3]Kwang-Jow Gan, Dong-Shong Liang:
Investigation of Adjustable Current-Voltage Characteristics and Hysteresis Phenomena for Multiple-Peak Negative Differential Resistance Circuit. IEICE Trans. Electron. 93-C(4): 514-520 (2010) - [j2]Kwang-Jow Gan, Dong-Shong Liang, Yan-Wun Chen:
Novel Multiple-Valued Logic Design Using BiCMOS-Based Negative Differential Resistance Circuit Biased by Two Current Sources. IEICE Trans. Inf. Syst. 93-D(8): 2068-2072 (2010)
2000 – 2009
- 2009
- [j1]Dong-Shong Liang, Kwang-Jow Gan, Cheng-Chi Tai, Cher-Shiung Tsai:
Standard BiCMOS Implementation of a Two-Peak Negative Differential Resistance Circuit with High and Adjustable Peak-to-Valley Current Ratio. IEICE Trans. Electron. 92-C(5): 635-638 (2009) - [c8]Dong-Shong Liang, Kwang-Jow Gan, Jenq-Jong Lu, Cheng-Chi Tai, Cher-Shiung Tsai, Geng-Huang Lan, Yaw-Hwang Chen:
Multiple-Valued Memory Design by Standard BiCMOS Technique. CSIE (3) 2009: 596-599 - 2008
- [c7]Dong-Shong Liang, Kwang-Jow Gan:
New D-Type Flip-Flop Design Using Negative Differential Resistance Circuits. DELTA 2008: 258-261 - 2006
- [c6]Dong-Shong Liang, Cheng-Chi Tai, Kwang-Jow Gan, Cher-Shiung Tsai, Yaw-Hwang Chen:
Design of AND and NAND Logic Gate Using NDR-BASED Circuit Suitable for CMOS Process. APCCAS 2006: 1325-1328 - [c5]Kwang-Jow Gan, Dong-Shong Liang, Cher-Shiung Tsai, Yaw-Hwang Chen, Chun-Ming Wen:
Five-State Logic Using MOS-HBT-NDR Circuit by Standard SiGe BiCMOS Process. APCCAS 2006: 1476-1479 - [c4]Dong-Shong Liang, Yaw-Hwang Chen, Chun-Min Wen, Chun-Da Tu, Kwang-Jow Gan, Cher-Shiung Tsai:
The Design of MOS-NDR-Based Cellular Neural Network. IJCNN 2006: 1033-1035 - 2005
- [c3]Dong-Shong Liang, Kwang-Jow Gan, Long-Xian Su, Chi-Pin Chen, Chung-Chih Hsiao, Cher-Shiung Tsai, Yaw-Hwang Chen, Shih-Yu Wang, Shun-Huo Kuo, Feng-Chang Chiang:
Four-Valued Memory Circuit Designed by Multiple-Peak MOS-NDR Devices and Circuits. IWSOC 2005: 78-81 - [c2]Dong-Shong Liang, Kwang-Jow Gan, Chung-Chih Hsiao, Cher-Shiung Tsai, Yaw-Hwang Chen, Shih-Yu Wang, Shun-Huo Kuo, Feng-Chang Chiang, Long-Xian Su:
Novel Voltage-Controlled Oscillator Design by MOS-NDR Devices and Circuits. IWSOC 2005: 372-375 - [c1]Kwang-Jow Gan, Dong-Shong Liang, Chung-Chih Hsiao, Shih-Yu Wang, Feng-Chang Chiang, Cher-Shiung Tsai, Yaw-Hwang Chen, Shun-Huo Kuo, Chi-Pin Chen:
Logic Circuit Design Based on MOS-NDR Devices and Circuits Fabricated by CMOS Process. IWSOC 2005: 392-395
Coauthor Index
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