"A Novel BIST Algorithm for Low-Voltage SRAM."

Zhikuang Cai et al. (2019)

> Home

Details and statistics

DOI: 10.1109/ITC-ASIA.2019.00036

access: closed

type: Conference or Workshop Paper

metadata version: 2019-11-12

- view
  - electronic edition via DOI
  - unpaywalled version
  authority control:
- export record
  dblp key:
  - conf/itc-asia/CaiWLLW19
- ask others
- share record
  persistent URL:
  - https://dblp.org/rec/conf/itc-asia/CaiWLLW19
Zhikuang Cai, Ying Wang, Shihuan Liu, Kai Lv, Zixuan Wang:
A Novel BIST Algorithm for Low-Voltage SRAM. ITC-Asia 2019: 133-138

manage site settings

To protect your privacy, all features that rely on external API calls from your browser are turned off by default. You need to opt-in for them to become active. All settings here will be stored as cookies with your web browser. For more information see our F.A.Q.