"Area-Efficient Pipelined VLSI Architecture for Polar Decoder."

Weihang Tan et al. (2020)

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DOI: 10.1109/ISVLSI49217.2020.00071

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type: Conference or Workshop Paper

metadata version: 2020-08-12

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Weihang Tan, Antian Wang, Yunhao Xu, Yingjie Lao:
Area-Efficient Pipelined VLSI Architecture for Polar Decoder. ISVLSI 2020: 352-357

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