"A Cascaded PLL (LC-PLL + RO-PLL) with a Programmable Double Realignment ..."

Tsung-Hsien Tsai et al. (2022)

> Home

Details and statistics

DOI: 10.1109/ISSCC42614.2022.9731676

access: closed

type: Conference or Workshop Paper

metadata version: 2022-03-21

- view
  - electronic edition via DOI
  - unpaywalled version
  authority control:
- export record
  dblp key:
  - conf/isscc/TsaiSHCCS22
- ask others
- share record
  persistent URL:
  - https://dblp.org/rec/conf/isscc/TsaiSHCCS22
Tsung-Hsien Tsai, Ruey-Bin Sheen, Sheng-Yun Hsu, Ya-Tin Chang, Chih-Hsien Chang, Robert Bogdan Staszewski:
A Cascaded PLL (LC-PLL + RO-PLL) with a Programmable Double Realignment Achieving 204fs Integrated Jitter (100kHz to 100MHz) and -72dB Reference Spur. ISSCC 2022: 1-3

manage site settings

To protect your privacy, all features that rely on external API calls from your browser are turned off by default. You need to opt-in for them to become active. All settings here will be stored as cookies with your web browser. For more information see our F.A.Q.