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Sheng-Yun Hsu

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2022
[c1]
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  - https://dblp.org/rec/conf/isscc/TsaiSHCCS22
Tsung-Hsien Tsai, Ruey-Bin Sheen, Sheng-Yun Hsu, Ya-Tin Chang, Chih-Hsien Chang, Robert Bogdan Staszewski:
A Cascaded PLL (LC-PLL + RO-PLL) with a Programmable Double Realignment Achieving 204fs Integrated Jitter (100kHz to 100MHz) and -72dB Reference Spur. ISSCC 2022: 1-3

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