"A reconfigurable distributed all-digital clock generator core with SSC and ..."

Y. William Li et al. (2012)

> Home

Details and statistics

DOI: 10.1109/ISSCC.2012.6176934

access: closed

type: Conference or Workshop Paper

metadata version: 2017-05-17

- view
  - electronic edition via DOI
  - unpaywalled version
  authority control:
- export record
  dblp key:
  - conf/isscc/LiOKLRS12
- ask others
- share record
  persistent URL:
  - https://dblp.org/rec/conf/isscc/LiOKLRS12
Y. William Li, Carlos Ornelas, Hyung Seok Kim, Hasnain Lakdawala, Ashoke Ravi, Krishnamurthy Soumyanath:
A reconfigurable distributed all-digital clock generator core with SSC and skew correction in 22nm high-k tri-gate LP CMOS. ISSCC 2012: 70-72

manage site settings

To protect your privacy, all features that rely on external API calls from your browser are turned off by default. You need to opt-in for them to become active. All settings here will be stored as cookies with your web browser. For more information see our F.A.Q.