"13.2 A 32Gb 8.0Gb/s/pin DDR5 SDRAM with a Symmetric-Mosaic Architecture in ..."

IkJoon Choi et al. (2024)

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DOI: 10.1109/ISSCC49657.2024.10454327

access: closed

type: Conference or Workshop Paper

metadata version: 2024-03-19

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  - conf/isscc/ChoiHKHWKCLLJJHYLYLOLLKKPHNCLLSLRSPLB24
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IkJoon Choi, Seunghwan Hong, Kihyun Kim, Jeongsik Hwang, Seunghan Woo, Young-Sang Kim, Cheongryong Cho, Eun-Young Lee, Hun-Jae Lee, Min-Su Jung, Hee-Yun Jung, Ju-Seong Hwang, Junsub Yoon, Wonmook Lim, Hyeong-Jin Yoo, Won-Ki Lee, Jung-Kyun Oh, Dong-Su Lee, Jong-Eun Lee, Jun-Hyung Kim, Young-Kwan Kim, Su-Jin Park, Byung-Kyu Ho, Byongwook Na, Hye-In Choi, Chung-Ki Lee, Soo-Jung Lee, Hyunsung Shin, Young-Kyu Lee, Jang-Woo Ryu, Sangwoong Shin, Sungchul Park, Daihyun Lim, Seung-Jun Bae, Young-Soo Sohn, Tae-Young Oh, SangJoon Hwang:
13.2 A 32Gb 8.0Gb/s/pin DDR5 SDRAM with a Symmetric-Mosaic Architecture in a 5^th-Generation 10nm DRAM Process. ISSCC 2024: 234-236

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