"A 32nm CMOS all-digital reconfigurable fractional frequency divider for LO ..."

Kailash Chandrashekar et al. (2012)

> Home

Details and statistics

DOI: 10.1109/ISSCC.2012.6177048

access: closed

type: Conference or Workshop Paper

metadata version: 2017-05-17

- view
  - electronic edition via DOI
  - unpaywalled version
  authority control:
- export record
  dblp key:
  - conf/isscc/ChandrashekarPMRP12
- ask others
- share record
  persistent URL:
  - https://dblp.org/rec/conf/isscc/ChandrashekarPMRP12
Kailash Chandrashekar, Stefano Pellerano, Paolo Madoglio, Ashoke Ravi, Yorgos Palaskas:
A 32nm CMOS all-digital reconfigurable fractional frequency divider for LO generation in multistandard SoC radios with on-the-fly interference management. ISSCC 2012: 352-354

manage site settings

To protect your privacy, all features that rely on external API calls from your browser are turned off by default. You need to opt-in for them to become active. All settings here will be stored as cookies with your web browser. For more information see our F.A.Q.